• 专利附录
  • 专利说明
  • 权利要求
  • 类似技术
  • 同族专利
  • 引用文献
  • 法律状态
  • 优先权
    • 专利摘要:
    The invention relates to radio engineering. The purpose of the invention is to provide protection against errors when eliminating duplicate blocks of information received without errors. The system contains at the transmitting station 1: rr 2 code words, parallel-to-serial converter (П) 3, control unit 4, series-parallel P 5 and modem 6, and at receiving station 7: receiver 8 code words, serial-parallel P 9, modem 10, parallel-serial P 11 and control unit 12, and also includes a telephone line 13. The mode of operation of the system with an error protection procedure consists of seven stages. In the first stage, the search for the first non-zero symbol loaded through P 9 into the receiver 8 is performed. In the second and third stages, parity error processing is performed. At the fourth stage, the byte "17" of the code word is received. In the fifth and sixth stages, the receiver 8 is searched for the first and second symbols of the resynchronization sequence, respectively. At the seventh stage, the comparison of the received symbols is performed. 3 il.
    公开号:SU1521297A3
    申请号:SU833547558
    申请日:1983-02-03
    公开日:1989-11-07
    发明作者:Ботрель Жоз；Арари Сами；Бриер Жозеф；Лувель Бернар
    申请人:Лъ Эта Франсэ Репрезанте Пар Ле Министр Де Птт /Сантр Насьональ Дъэтюд Де Телекоммюникасьон/(Фирма)；Этаблиссман Пюблик Де Диффюзьон Ди Теледиффюзьон Де Франс (Фирма)；
    IPC主号:
    专利说明:

    The invention relates to radio engineering and can be used in data transmission systems using a switched telephone network.
    The purpose of the invention is to provide protection against Errors when eliminating repetitions of blocks of information received without errors.
    Figure 1 shows a structural electrical circuit of the proposed system; figure 2 - code generator
    words, option of performance; FIG. 3 shows a code word receiver, an embodiment.
    The asynchronous two-way data transmission system contains (Fig. 1) at the transmitting station 1 a generator 2 code words, a parallel-serial converter 3, a control unit 4, a serial-parallel converter 5, a modem 6 at the receiving station 7, a receiver 8 codeo C
    VC words, serial-parallel converter 9, modem 10, parallel-serial converter 11, control unit 12, the receiving and transmitting sides being connected by telephone line 13.
    The code word generator 2 contains (FIG. 2) a parity generator 14, an input register 15, a selection block 16, a clock generator 17, a counter 18, a zero byte register 19, a coefficient storage register 20, a division remainder accumulation register 21, an arithmetic unit 22, a buffer register 23, a drive 24, first to fourth read blocks 25-28, auxiliary register 29, also shows the first register 30 with the first and second E-bits of 31 and 32 ,. second register 33 with two binary bits 34 and 35, additional counter 36, from the third to fifth registers 37-39 ..
    The code word receiver 8 contains (FIG. 3) a drive 40, a read block 41, an error accumulator register 42, a comparator 43, a clock generator 44 division counter 45, a selection block 46 for auxiliary register 47, an input register 48, a counter 49 for coded words, the arithmetic logic unit 50, the buffer register 51, the coefficient accumulation register 52, the division balance accumulation register 53, the mask accumulation register 54, also shows the first trigger 55, the first register 56 with binary bit 57, the second register 58 with binary bits 59- 63, third to fifth registra 64-66, second trigger 67. ..
    The system works as follows.
    In the initial state on the transmitter
    1 and receiving 7 stations in the generator
    2 and receiver 8 (FIG. 1), the binary bits 34 and 57 of the second and first registers 33 and 56 (FIGS. 2 and 3) are in the O state, which implies transmission without a procedure.
    At the control input of the generator 14, there is 1 and it successively transmits, after calculating the parity, to its output through the input register 15, the symbols transmitted to it via the data bus (Fig. 2).
    An operation mode without a procedure is used to run in receiver 8 on
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    receiving station 7 activation start receiving code words transmitted according to the procedure. Transmitting station 1 begins to transmit without a procedure some sequence of predetermined bytes of the type of sequence ESC, 3 / A, 6/9, 474, denoted hereinafter simply by the sequence D1K.
    In receiver 8 (FIG. 3), the bit 57 of the first register 56 is still in the state O. The output of the input register 48 is directly connected to its output bus. Consequently, the LH sequence is directly applied to control unit 12. When control unit 12 recognizes the D1K sequence, it sets 1 bit 57 in the first register 56 and using a parallel-to-serial converter 1 1, modem 10 of the telephone line 13, modem-6 at the transmitting station 1, and a serial-parallel converter 5 sends, in response to block 4-control, another sequence of predetermined bytes such as sequence ESC, 3 / A, 7/3 and plus the byte of the operating state of receiving station 7; this sequence is referred to hereinafter simply as the AR sequence, which serves to confirm reception. The configuration of the state byte of the operating mode of the receiving station 7 is such that it contains a binary bit of a certain rank or weight of the type of discharge of PZ, which is in state 1 and indicates that the procedure now operates at the receiving station 7. Other bits of the status byte, with the exception of the parity check bit B8, may represent information on other functions of the receiving station 7.
    Upon receiving the AR sequence, block 4 sets to 1 bit 34 of the second register 33 in generator 2,
    The control unit 4 checks the binary bit 32 of the first register 30, which must be in 1 in order for the byte to be transmitted to the generator 14 via the data engine. Recall that the clock generator 17 using the second block 26 knows the first address of the drive 24, for
    which corresponding bits of AH and DOR are equal to O.
    Then block 4 transmits a symbol of seven binary bits on the data bus to generator 14, suppose that at this moment the bits are not zero. In generator 14, a binary bit parity check is calculated in par. it is added to the seven first bits to form a byte transmitted to the input register 15. Now the bit 32 of the first register 30 is set to O from the clock generator 17 to prohibit the arrival of the New Byte. The clock generator 17 selects the contents of the input register 15 and the fifth register 39 as operands A and B of the arithmetic logic unit 22. The result of the inequality is checked by the clock generator 17, which, through the control input, selects in the arithmetic logic unit 22 an operation F A, then loading output signal F to the buffer register 23. The contents of the buffer register 23 are loaded into the drive 24 at the current address from the first and second read blocks 25 and 26. Note that during recent operations, the contents of the input register 15 remain unchanged.
    If the character transmitted by control block 4 is zero and if it corresponds to the first byte formed in the code word, the detection of equality A B in the clock generator 17 causes the last bit to be set to 32 in 1 and the accumulator 24 is not loaded.
    After loading the first byte of the code word into the drive 24, its division into the forming polynomial begins. To this end, the clock generator
    17 selects the contents of register 21, zero at this moment, as operand B, then executes the F A © B operation and loads into the counter
    18V value. Then the clock generator 17 loads the result F into the buffer register 23, deactivates the control input of generator 1A to prevent parity, and loads the contents of buffer register 23 into the input register 15 through generator 14. The binary bit value 8 of the input register 15 is checked clock generator 17. If it is equal to 1, then the clock generator 17 is selected
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    em the contents of the input register 15 c. register 20 as the new operands A and B of the arithmetic logic unit 22, performs the operation F А + В, then loads the result into the buffer register 23, then again into the input register 15. Now the input register 15 is shifted to the left with the introduction of O into bit d1 If during the preceding check of the binary bit in the contents of the input register 15 it was found that it is equal to O, then the above left shift is effectively performed. Then the contents of counter 18 are decremented by one, and the binary bits of the input register 15 are checked again and so on until the contents of counter 18 become zero.
    At this point, the contents of the first interchange unit 25 receive an increment per unit and its contents are checked.
    If it is less than 6, then the clock generator 17 selects the contents of the input register 15 as operand A for the arithmetic logic unit 22, then performs the operation FA, loads the result into the buffer register 23, then into register 21, then determines the parity validity in generator 14 and installs a binary bit 32 in 1, which allows the transfer of a new USvol from block 4 to the input register 15.
    If it is found that the contents of the first read block 25 is equal to 16, then the contents of the input register 15 are shifted to the right by issuing a command to the right-shift control input with the input O in b8. Then the clock generator 17 selects the contents of the input register 15 as an operand. A, performs the operation F A, checks the accuracy of the parity calculation in the generator 14, loads the result from F into the buffer register 23, transfers the contents of the buffer register 23 to the input register 15 through the generator 14, which calculates the binary bit B8 of the 16th byte code the words. Then, the clock generator 17 performs the operation F A, then loads the result F via the buffer register 23 into the drive 24 at the current address from the first and second blocks 25. and 26 read F 16. Then the binary AE of the drive 24 at the address from
    the second block 26 is set to I, indicating that the sixteen first bytes of the code word are in the accumulator 24, thereafter, the first link 25 is set to 1 and the second block 26 is received a single increment. Finally, the binary bit 32 of the first register 30 is set to 1, allowing the input of a new character from the seven binary () bit from the control block 4 to the input register 15.
    In the absence of a request to repeat the binary bit 35 of the second register 38 is equal to O. The clock generator 17 checks the control input, which is equal to indicating that the transmission of the generator 2 to the parallel-serial converter 3 is enabled. Then, at the address of the fourth reading unit 28, whether the AE check DOK is equal here does not make sense, since there is no request for repetition; then the contents of the additional account 36 are checked, which for the same reason is equal to O.
    The content of the third read block 27 is checked and it is found to be less than 17,
    which entails consistent
    the loading of the sixteen first bytes of the code word from the accumulator 24 to the address located in the third and fourth blocks 27 and 28 and the third block 27 of the slot receives a single increment with Kazzda loading.
    When the content of the third read block 27 is equal to 17, the contents of the zero byte register 19 is loaded into the parallel-sequential converter 3, i.e. The 17th character of the code word is transmitted. Then, in the accumulator 24, the binary bit flOR of the address of the fourth block 28 is set to 1, while the binary bit AE of the same address is set to OV. However, the third read block 27 is set
    appears in 1 and the fourth block 28 receives a single increment. The AE element of the current address of the fourth read block 28 is checked. If it turns out to be O, then the binary bit DOR of the same address is set to O.
    Suppose the code word is not properly received at receiving station 7 and then you need to repeat it.
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    from the transmitting station 1. First of all, it should be noted that the counter 49 at the receiving station 7 counts the received code words modulo 16. Therefore, the control unit 12 knows which number to give to each codeword, this number corresponds to its address of the fourth unit 28 in the storage unit 24 of the generator 2.
    For the replay code, block 12 transmits 1 sequence to the transmitter side: NAK, NVMMOT, where NAK is the character corresponding, CCITT recommendation code 5 and NVMMOT, is the contents of counter 49 plus parity; This content identifies an incorrectly received word.
    Upon receipt of this request, block 4 loads the four binary low-order bits of the received NVHMOT character into auxiliary register 29 via the dan bus, then sets 1 binary bit 35 of the second, register 33. Recall that in drive 24 for each transmitted code word, binary the DOR element is set to 1, and the binary bit bit AE is set to O.
    The clock generator 17 then conducts a binary bit test of the DR and detects that it is equal to 1, which entails checking the binary bit of the DOC of the drive 24. The clock generator 17 performs the addressing of the drive 24 through the auxiliary register 29. If the DOC is 1, then this indicates that the code word with address X is part of the repeated region. Next will be presented and other specific cases.
    After the check is positive, the contents of the auxiliary register 29 are loaded into the fourth register 2B. The clock generator 17 sets an additional counter 36 to 1, loads the fourth block 28 into 1 and 1, and resets the binary bit 35 of the second register 33 to O. If the check is negative, the contents of the fourth block 28 do not change, but the clock generator 17 also sets the additional the counter 36 is in 1, loads 1 into the third block 27, and resets the binary bit 35 to O.
    Then it is checked whether generator 2 can transmit, i.e. as before, it is checked whether it is set to up5
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    error shields. This mode of operation contains seven stages.
    The first stage consists in finding the first non-zero character loaded via serial-to-parallel converter 9 to receiver 8. This character is the first byte of the expected codeword, which starts the second stage.
    The clock generator 44 selects the contents of the receiver 8 and the fifth register 66 as operands A and B for the arithmetic logic unit 50. Upon receiving the first nonzero byte, the output of the arithmetic logic unit 50 goes to the state O, as a result the clock generator 44 loads 1 in block 4 and the receiver 8 goes into the second stage.
    In the second stage, the state of the binary bit 60. the second register 58 is checked. In case of a parity error, the first trigger 55 and, if necessary, the second trigger 67 come into operation, while the register 42 loads the value reached in block 4 at the time change the state of the first and second triggers 55 and 67.
    The contents of auxiliary register 47 and input register 48 are transferred to drive 40 at the location indicated by block 41, then it gets a single increment. To perform this operation, the clock generator 44 selects the contents of the input register 48 as operand A in the arithmetic logic unit 50, then performs operation F A, then the result F is loaded into the buffer register 51, then into drive 40, at the address specified by block 41.
    Then the contents of the input register 48 undergoes polynomial division by the polynomial C (k) and the remainder of the section is stored in register 53. When the contents of block 41 reach 16, receiver 8 goes to third agap.
    All of the above operations are carried out in a sequential manner. The co-maintained input register 48 always remains operand A of arithmetic logic unit 50, clock generator 44 selects the contents of registers 52 and 53 as operand B, then F A ® B is executed. In division counter 45, the value 6 is loaded. . Then; result F is loaded into bu
    Fern register 51 and in the input register 48.
    If the binary bit b8 of the contents of input register 48 is 1, then the contents of input register 48 and register 52 are selected as operands A and B for the arithmetic logic unit 50, where the operation F A B is performed. Then the result F is loaded into the buffer register 51 then to the input register 48. Finally, using the left shift control input, the contents of the input register 48 are shifted to the left and O is entered as a binary digit in 1.
    If the binary bit in the content of input register 48 is equal to O instead of 1, as previously assumed, go directly to the left shift.
    The content of division counter 45 is reduced by one, and is checked. As long as its contents are different from. About, they return to their former functioning. As soon as its content becomes equal to O in arithmetic logic unit 50, operation F A is allowed, and the result F is loaded into buffer register 51 and then from buffer register 51 into register 53.
    Then the contents of block 41 are checked. If it is not 16, return to the beginning of the second stage. When it becomes equal to 16, move to the third stage, as previously indicated.
    In the third stage, the parity error handling is identical to the processing in the second stage. The division algorithm is applied to byte 16, but the byte itself is not inserted into the accumulator 40. Only the remainder of the division, i.e. final residue.
    Under normal conditions, the 16th character is loaded into the input register 48, then shifted to the left to eliminate the binary bit of parity using the input control of the left shift control dg, and in: the bit into the input O. Then the contents The e of the INPUT register 48 and the register 53 are selected as operands A and B for the arithmetic logic unit 50, and the command is received for transmitting F А + B. The result from F is loaded into the buffer register 51, then into the input register 48, containing
    the equal input I, then at the address of the fourth block 28, the binary bit DOR is set to 1 or the binary bit AE to 1.
    Suppose the previous test was positive; check the additional counter 36, which is located at 1, which entails
    is the selection of loading the contents of the third register 37 into the parallel-serial converter 3 through the output of the generator 2, then installing the contents of the additional counter 36 into 2. Then, during the execution of the program for the subsequent transfer of the clock generator 17, the binary bit of the DC is checked and detected O, then the control input, the binary bits of the MLC or AE for the existence of 1 and an additional counter 36 by 2, which entails the choice of loading the contents of the fourth register 38 into a parallel-serial converter 3 and 3 in the installation of additional counter 36. In a subsequent execution of the program transmission is t, that an additional counter 36 is set to 3, which causes register 19 to load content selection parallel-serial converter 3, i.e., the number of the code word to be transmitted, which should serve as a link for the code words for the receiving station 7. Finally, additional counter 3 is set to O.
    Note that at the end of the transfer of the code word of the address M10TE, the fourth block 28 should be loaded according to the auxiliary register 29 or its contents should remain unchanged; normally, this pointer receives a single increment, from which it can be said that subsequent code words have been transmitted, which may have already been transmitted.
    Each pairing to send a byte through a parallel-to-serial converter 3, which may be a code word byte or a synchronization recovery sequence byte, may be followed by a sahHCb byte entering the accumulator 24 from block 4 and its processing.
    If, after the parcel, check the binary bits of the AE and DOYA drive 24 at the address from the second block 26 and address

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    521297ш
    Since a binary digit of 32 gives a result, equal to 1, the recording does not occur and returns to the beginning of the sending program.
    In the case of working with transmission activation with the procedure, no special synchronization sequence is required, and the exchange of D1K and AR messages clearly indicates that, after the receiving station exchanges 7, the first non-zero byte is the first byte of the first codeword.
    To stop transmission, procedure 4 sends the sequence ESC, 3 / A, 6 / A, 4/4; It goes without saying that this sequence is processed in generator 2. After receiving this sequence, unit 4 sets the binary bit 34 of the second register 33 to O, and the receiving party sends an AR sequence in which the status byte has a binary bit OE A. Accepting this sequence, unit 4 resets the binary bit 34 of the second register 33 to O.
    At the initial moment of transmission, the receiver, 8 operates without error protection. When the control signal from the serial-parallel converter 9, pointing to the corresponding symbol, goes to a high level, the control signal changes to the serial-parallel converter 9, sets the reliability of the output signals and resets control signal to O.
    Now the input register 48 is loaded with the byte detected on the UXO-Ds of the serial-parallel converter 9, and the parity error detection signal transmitted through it is repeated in the second register 58 for composing. there is a binary bit 60. Then, the control signal is set to O and the binary bit 61 of the second register 58 is set to 1.
    The input register 48 is connected via the output using block 12 and the binary bit 61 is reset to O.
    35
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    The cycle continues until block 12 recognizes the LH message and sets the binary bits 57 and 59 to 1. Now there is a perb - a move to the operating mode of the procedure is not performed and the request for repetition is received. Then go to t processing III.
    Iii. Symbol 17 is zero and there are some parity errors, the second trigger 67 is in 1, or the symbol 17 differs from the contents of the fifth register 66, or the processing roar II, or the symbol 17 is zero, the first trigger 55 is in G, but Register 53 is the one that is shifted to the right with control on the shift control input to the right dc, and o is entered in bit b8. After that, the operation FA is performed, the result from F is loaded into the buffer register 51, then into the register 53. Then proceed to the fourth stage.
    The fourth stage corresponds to the result in block 41 different from the result of byte 17 of the code word. One J5 with a yule value, or, finally, the symbol 17 of the three following types of signals is implemented in the register 42, mentioned above, the vibrability from the values of byte 17, the remainder of the contents of register 53 and the number of characters received with erroneous parity is zero, the first flip-flop 55 ki I, II, and III. is in O and the contents of the register. Symbol 17 is zero, jia 53 is not zero. the contents of register 53 is well. Then the contents of counter 49 are left-handed and there are no errors on the even-20 load in the auxiliary register, i.e. the first and second triggers 55 47, the binary bit 62 of the second re and 67 are in the state O.
    Part of the counter 49 receives a single increment, the first and second triggers 55 and 67, the registers 42, 54 and 53 25 are licensed. Then, the receiver 8 goes to reset to O, the block 41 initiates the five stage, is lysed to 1, and the binary bit 63 of the second register 58 is set to 1.
    Now, block 12 should read n m-zO of the repeated code word. From this, there are eleven information bytes, the post- block of block 12 periodically scanned to drive 40 before the parallel-serial converter transmits a new character.
    the 58 is set to 1. The first and second triggers 55 and 67 and the registers 42, 54 and 53 re-initiate. The transmission on request for the repetition is performed by block 12 which has a character containing the number of the binary digit 62 of the second register 58. The transfer of the binary bit
    can lead to
    62 to state 1
    The recci is not produced and a request for repetition is received. Then go to t processing III.
    Iii. Symbol 17 is zero and there are some parity errors, the second trigger 67 is in 1, or the symbol 17 differs from the contents of the fifth register 66, or the processing roar II, or the symbol 17 is zero, the first trigger 55 is in G, but The register 53 is the result in block 41, which is different from the result in register 42, mentioned above with a yule, or, finally, the symbol 17 is zero, the first flip-flop 55 is in O, and the contents of the register 53 is not zero. Then the contents of the counter 49 is loaded into auxiliary register 47, the binary bit 62 of the second register
    licking. Then receiver 8 goes to the fifth stage,
    gist 58 is set to 1. The first and second triggers 55 and 67 and registers 42, 54 and 53 are reinitialized. Then receiver 8 goes to the fifth stage,
    The repeat request transmission is performed by block 12 which has a character containing the number of the code word to be repeated. With this purpose, block 12 periodically views
    binary bit 62 of the second register 58. Binary bit transition
    can lead to
    62 to state 1
    Ii. Symbol 17 is zero, interruption of the program in block 12, g, г ™ P.
    the contents of register 53 are different from O and there is only one parity error, the first trigger 55 is in state 1 and the second trigger 67 is in state O. Next comes the execution of the erroneous binary search algorithm.
    As a result of the search, block 41 receives the address of the erroneous byte, and register 54 receives the mask for correction.
    The equality between the contents of block 41 and register 42, fixed by comparator 43, makes it possible to carry out flax and

    At the fifth stage, the receiver 8 finds in the search for the first symbol of the re-synchronization sequence, i.e. after sending a request for retransmission, it searches for the corresponding SYN symbol.
    Upon detection of the SYN character, i.e. The symbol dc, the contents of which is in the third register 64, the binary bit 62 is reset to O and the receiver 8 proceeds to the sixth stage.
    At the sixth stage, the received symbol
    There is no correction, and JQ is processed according to the type of processing I. Otherwise, a request is made to repeat.
    Indeed, the rank of an erroneous binary bit in the sequence S of the coefficients of the polynomial S (x) is shifted to the seventh stage, otherwise given by the value of the indicator p, and in x the binary bit 62 in the second R (x) modulo G (x) . However, if this binary bit does not belong to a broken parity byte,
    compared with the contents of the fourth register 65 to find the second SYN symbol of the resynchronization sequence.
    If there is equality, receiver 8
    register 58 is set to VI, then returns to the fifth stage.
    .
    equal flax and

    At the fifth stage, the receiver 8 is in search of the first symbol of the re-synchronization sequence, i.e. after sending a retransmission request, it searches for the corresponding SYN character.
    Upon detection of the SYN character, i.e. the character whose contents are in the third register 64, binary bit 62 is reset to O and; receiver 8 goes to the sixth stage.
    At the sixth stage, the received symbol
    proceeds to the seventh stage, otherwise the binary bit 62 in the second
    compared with the contents of the fourth register 65 to find the second SYN symbol of the resynchronization sequence.
    If there is equality, receiver 8
    proceeds to the seventh stage, otherwise the binary bit 62 in the second
    register 58 is set to VI, then returns to the fifth stage.
    In the seventh stage, the received symbol must be centered on the contents of the counter 49. If so, receiver 8 goes to the first stage, if not, the binary bit 62 is set to I and it returns to the fifth stage.
    权利要求:
    Claims (1)
    [1]
    Invention Formula
    An asynchronous two-way data transfer system between the transmitting and receiving stations, comprising a control unit at the transmitting station, connected to a series-parallel converter and a code word generator, which is connected to a parallel-serial converter, which is connected to a modem connected to a series-parallel converter, and at the receiving station - a modem connected to a series-parallel converter, which is connected to the receiver of code words, and with a parallel o-serial converter, which is connected to the control unit and the receiver of code words, different from the fact that, in order to provide error protection when eliminating duplicate blocks of information received without errors, the code word generator at the transmitting station contains the parity generator, outputs which are connected to the signal inputs of the second register, the output of which is connected to one input of the arithmetic logic unit, the other input and output of which are connected respectively
    with memory register and clock generator, outputs
    a coefficient that is connected to the output of the accumulation register of the remainder of the division, and with the input of the buffer register, the output of which is connected to the input of the parity generator, to the input of the register of the accumulation of the remainder of the division and one input of the accumulator, the other inputs of which are connected to the outputs of the converting units, the output of the accumulator output of the code generator.
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    words and connected to the output of the input register and the register of the zero byte register, and the clock generator, the outputs of which are connected to the clock inputs of the parity generator, the input register and the counter, while the information inputs of the code word generator are the inputs of the selection unit, the input of the parity generator and the input an auxiliary register, the output of which is connected to the input of the corresponding block of the gateway, the output of which is connected to the output of the accumulator, and at the receiving station the receiver of code words contains the input register, the output which is connected to one input of an arithmetic logic unit, the other input and output of which are connected respectively to the output of the coefficient accumulation register, which is connected to the output of the accumulation register of the division remainder and the output of the mask accumulation register, and to the input of the buffer register, the output of which is connected to the input of the input register , with the input of the accumulation register of the remainder of the division and one input of the accumulator, the other input of which is connected to the output of the readout unit, the output of the accumulator is connected to the output of the input register which d is the output of the receiver code words whose inputs are selection inputs of input register unit and the input of which is connected to the input of the auxiliary register kotorogo.soedinen output to one input of an arithmetic logic unit, connected in series de5 counter
    which are connected to the clock inputs of the input and auxiliary registers, the output of the readout unit is connected to one input of the comparator and the input of the error accumulation register, the output of which is connected to another input of the compressor, and the counter of the encoded words, the output of which is connected to another input arithmetic logic unit.
    ig. {
    Fig.Z
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    同族专利:
    公开号 | 公开日
    JPS58196744A|1983-11-16|
    NO161649B|1989-05-29|
    FR2520956B1|1984-05-04|
    NO830357L|1983-08-05|
    DE3376726D1|1988-06-23|
    CA1223934A|1987-07-07|
    EP0086128A1|1983-08-17|
    DK43183D0|1983-02-03|
    BR8300634A|1983-11-08|
    US4551839A|1985-11-05|
    NO161649C|1989-09-06|
    FR2520956A1|1983-08-05|
    DK43183A|1983-08-05|
    EP0086128B1|1988-05-18|
    ES8401291A1|1983-12-01|
    ES519495A0|1983-12-01|
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    FR2261666B1|1974-02-19|1979-09-28|Thomson Csf|
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    DE2914665C2|1979-04-11|1986-04-17|Standard Elektrik Lorenz Ag, 7000 Stuttgart|Telecommunication system, in particular video text system, as well as partially centralized and decentralized circuit module for this system|
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    US4422171A|1980-12-29|1983-12-20|Allied Corporation, Law Department|Method and system for data communication|NL8403818A|1984-12-17|1986-07-16|Philips Nv|METHOD AND APPARATUS FOR DECODING INFORMATION FLOW PROTECTED BY A REED-SOLOMON CODE|
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    US20020159598A1|1997-10-31|2002-10-31|Keygen Corporation|System and method of dynamic key generation for digital communications|
    DE102004018541A1|2004-04-14|2005-11-17|Atmel Germany Gmbh|Method for selecting one or more transponders|
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    法律状态:
    优先权:
    申请号 | 申请日 | 专利标题
    FR8202120A|FR2520956B1|1982-02-04|1982-02-04|
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